A) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having at least capacitors and fuses and its manufacture method.
B) Description of the Related Art
A semiconductor device having a desired circuit can be manufactured by forming, on one surface of a semiconductor substrate, active components such as metal-oxide-semiconductor (MOS) field effect transistors (FETs) (hereinafter abbreviated to “MOSFET”) and passive components such as capacitors, resistors and fuses, and connecting these components by wiring lines.
Each circuit component is formed, for example, by depositing a mask having a predetermined pattern on a conductive film formed on a semiconductor substrate and etching and removing the conductive film not covered with the mask. Many processes are required to form circuit components of a single layer structure and a multi-layer structure.
It is desired to reduce the number of manufacture processes in order to improve the productivity and reduce the manufacture cost of semiconductor devices integrating various circuits. The number of processes has been reduced by commonly using some of processes of manufacturing a variety type of circuit components.
For example, Japanese Patent Laid-open publication No. SHO-60-261154 describes a semiconductor device wherein the gate electrode of a MOSFET and a fuse are formed by one patterning process.
Japanese Patent Laid-open publication No. HEI-2-290078 describes a semiconductor device wherein the lower electrode of a capacitor, a fuse and a wiring line are made of the same conductive layer.
Japanese Patent Laid-open publication No. HEI-6-283665 describes a self-protective decoupling capacitor wherein the upper electrode and a fuse are formed by one patterning process.
Japanese Patent Laid-open publication No. HEI-7-130861 describes a semiconductor integrated circuit device wherein the gate electrode of MOSFET and a fuse are formed by one patterning process.
Japanese Patent Laid-open publication No. HEI-8-274257 describes a semiconductor device wherein the upper and lower electrodes of a capacitor, a resistor and the gate electrode of MOSFET are formed by one patterning process. In this example, the upper electrode of the capacitor has the two-layer structure and one patterning process is executed as a pre-process of forming the upper electrode of the two-layer structure.
Japanese Patent Laid-open publication No. HEI-11-195753 describes a semiconductor device wherein a MOS transistor and a capacitor are formed being coupled together unable to be separated, and the upper electrode (opposing electrode) or lower electrode of the capacitor and the resistor or fuse are formed by one patterning process.
Japanese Patent No. 3092790 discloses a method of forming a capacitor, a resistor and the gate electrode of MOSFET by two photolithography processes. With this method, after a conductive layer as the lower electrode of a capacitor is formed, a capacitor dielectric film is formed and patterned. Thereafter, a conductive layer as the upper electrode of the capacitor is formed. This conductive layer is made of two layers, a polysilicon layer and a metal silicide layer. An etching mask for leaving the upper electrode is formed and the conductive layer as the upper electrode is etched. This etching continues even after a portion of the capacitor dielectric film is exposed, to thereby pattern the conductive layer as the lower electrode.
The capacitor can therefore be formed by two lithography processes, the process of patterning the capacitor dielectric film and the process of patterning the upper electrode. The resistor is made of the same conductive layer as that of the lower electrode of the capacitor.
Japanese Patent Laid-open Publications Nos. SHO-60-261154, SHO-62-238658, HEI-4-365351, HEI-6-283665 and HEI-7-130861 disclose a fuse having a two-layer structure of polysilicon and metal silicide. This structure can lower the resistance of the fuse and prevent unexpected fuse breakdown.
Capacitors, MOSFETs and fuses are used together in various circuits such as a memory circuit, a voltage or current trimming circuit, and a defect relieving circuit (so-called redundancy circuit) capable of maintaining the circuit function even some portion has a defect.
A capacitor has at lease three layers, a lower electrode, a capacitor dielectric film and an upper electrode, excepting that a semiconductor substrate is used as the lower electrode. The numbers of layers of a MOSFET gate and a fuse are at least one.
Conventionally, a capacitor having at least three layers and a fuse having at least one layer have been formed by using at least three etching masks to pattern each layer, excluding the wiring process between the capacitor and fuse.
The number of processes can be reduced by reducing the number of etching masks used for semiconductor device manufacture. By reducing the number of processes, it becomes easy to improve the productivity and manufacture cost of semiconductor devices.